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- Path: informatik.tu-muenchen.de!fischerj
- From: fischerj@informatik.tu-muenchen.de (Juergen "Rally" Fischer)
- Newsgroups: comp.sys.amiga.programmer
- Subject: Re: CHIP RAM speed test resul
- Date: 15 Apr 1996 14:05:16 GMT
- Organization: Technische Universitaet Muenchen, Germany
- Distribution: world
- Message-ID: <4ktl2s$8tr@sunsystem5.informatik.tu-muenchen.de>
- References: <4j6jv0$1im@serpens.rhein.de> <5827.6659T112T770@mbox.vol.it> <1996Apr2.234528.8971@scala.scala.com> <4k1kk3$i2q@sunsystem5.informatik.tu-muenchen.de> <4k1oqk$aom@freenet-news.carleton.ca>
- NNTP-Posting-Host: hphalle5.informatik.tu-muenchen.de
- Originator: fischerj@hphalle5.informatik.tu-muenchen.de
-
-
- In article <4k1oqk$aom@freenet-news.carleton.ca>, de351@FreeNet.Carleton.CA (K. C. Lee) writes:
- |> Organization: The National Capital FreeNet
- |> Lines: 41
- |> Sender: de351@freenet2.carleton.ca (K. C. Lee)
- |> Message-ID: <4k1oqk$aom@freenet-news.carleton.ca>
- |> References: <4j6jv0$1im@serpens.rhein.de> <5827.6659T112T770@mbox.vol.it> <1996Apr2.234528.8971@scala.scala.com> <4k1kk3$i2q@sunsystem5.informatik.tu-muenchen.de>
- |> Reply-To: de351@FreeNet.Carleton.CA (K. C. Lee)
- |> NNTP-Posting-Host: freenet2.carleton.ca
- |>
- |>
- |> Juergen "Rally" Fischer (fischerj@Informatik.TU-Muenchen.DE) writes:
- |> >
- |> > ok, so why my 020 needs _12_ cycles , i.e. _846_ ns (!!!!) to load a
- |> > byte/.w/.l from chipmem ?
- |>
- |> Remember that the CPU is not the only one that have access to your chip
- |> ram... ( I don't know too much about AGA 64-bit fetch and all the funny
-
- This is not the reason. same goes for master dma off.
- This also won't explain why reads are slower than writes although the
- 020 can read in 6 cyles, i.e. beyond 8 cycles.
-
- |> screen modes.) Your CPU have 1/2 of the bandwidth available and also have
- |> to wait if it trys to access the memory at the wrong time.
- |>
- |> > that's unlogic, because any acess should be delayed by a fix amount
- |> > of time. but: load 6 -> 12 cycles (difference: 6), store 4 -> 8 cycles
- |> > (difference: 4).
- |>
- |> May be it is the memory access pattern ? I wouldn't even try to figure
- |> things in a CPU with caches.
-
- It is not the cache, my cpu got no datacache.
- Anyway, wrong results dues to caching would mean _faster_ results, not
- slower ;->
-
- |>
- |> > BTW imho it should cost almost nothing to add a A3000-alike chipmembuffer,
- |> > did you do it in walker ? I really hope so. 4 longwords would even
- |>
- |> What chip buffer is that ? The 020 already have 32-bit access to the chip
- |> ram.
-
- The A3000 has 32bit acess, too. but it is buffered so cpu can go on
- with fastmemacess while the write is done.
-
- |> > fischerj@Informatik.TU-Muenchen.DE (Juergen "Rally" Fischer) =:)
- |>
- |> K. C. Lee
- ------------------------------------------------------------------------
- fischerj@Informatik.TU-Muenchen.DE (Juergen "Rally" Fischer) =:)
-
-